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datasheet 5P49V5908 revision b 07/13/15 1 ?2015 integrated device technology, inc. programmable clock generator 5P49V5908 description the 5P49V5908 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data-communications applications. configurations may be stored in on-chip one-time programmable (otp) memory or changed using i 2 c interface. this is idts fifth generation of programmable clock technology (versaclock ? 5). the frequencies are generated from a single reference clock or crystal. two select pins allow up to 4 different configurations to be programmed and accessible using processor gpios or bootstrapping. the different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (us, japan, europe) or system production margin testing. the device may be configured to use one of two i 2 c addresses to allow multiple de vices to be used in a system. pin assignment features ? generates up to four independent output frequencies with a total of 11 differential outputs and one reference output ? supports multiple differential output i/o standards: ? three universal outputs pairs with each configurable as one differential output pair (lvds, lvpecl or regular hcsl) or two lvcmos outputs. frequency of each output pair can be individually programmed ? eight copies of low power hcsl(lp-hcsl) outputs. programmable frequency ? see output features and descriptions for details ? one reference lvcmos output clock ? high performance, low phase noise pll, <0.7 ps rms typical phase jitter on outputs: ? pcie gen1, 2, 3 comp liant clock capability ? usb 3.0 compliant clock capability ? 1 gbe and 10 gbe ? four fractional output dividers (fods) ? independent spread spectrum capability from each fractional output divider (fod) ? four banks of internal non-volatile in-system programmable or factory programmable otp memory ? i 2 c serial programming interface ? input frequency ranges: ? lvcmos reference clock input (xin/ref) ? 1mhz to 200mhz ? crystal frequency range: 8mhz to 40mhz ? output frequency ranges: ? lvcmos clock outputs ? 1mhz to 200mhz ? lp-hcsl clock outputs ? 1mhz to 200mhz ? other differential clock outputs ? 1mhz to 350mhz ? programmable loop bandwidth ? programmable crystal load capacitance ? power-down mode ? mixed voltage operation: ? 1.8v core ? 1.8v vddo for 8 lp-hcsl outputs ? 1.8v to 3.3v vddo for other outputs (3 programmable differential outputs and 1 reference output) ? see pin descriptions for details ? available in 48-pin vfqfpn package (ndg48) ? -40 to +85c industrial temperature operation 1 13 48-pin vfqfpn 43 31 xout xin/ref v ddo out10b out2 out9b out9 out2b v ddo 2 v dda sel1/sd sel0/scl v ddo out6 out6b out1b out1 v ddo 1 v dd v ddo out0_sel_i2cb epad 2 3 4 5 6 14 15 16 17 18 32 33 34 35 36 44 45 46 47 48 7 8 9 10 11 12 19 20 21 22 23 24 25 26 27 28 29 30 37 38 39 40 41 42 v ddo out8b out8 out7b out7 sd/oe v dd out5 out5b v ddo 4 out4 out4b oeb 3,11 oeb 7_10 nc out3 out3b v dd v dd_core nc nc nc out11b out11 out10 v ddo 0 oe_buffer
programmable clock generator 2 revision b 07/13/15 5P49V5908 datasheet functional block diagram applications ? ethernet switch/router ? pci express 1.0/2.0/3.0 ? broadcast video/audio timing ? multi-function printer ? processor and fpga clocking ? any-frequency clock conversion ? msan/dslam/pon ? fiber channel, san ? telecom line cards ? 1 gbe and 10 gbe xin/ref xout sd/oe sel1/sda sel0/scl v dda v ddo v ddo 0 out0_sel_i2cb v ddo 1 out1 out1b v ddo 2 out2 out2b v ddo 4 out4 out4b fod1 fod2 fod3 fod4 pll otp and control logic oe_buffer out3, 5, 6, 11 out7 - 10 oeb 7_10 oeb 3,11 v dd v dd_core
revision b 07/13/15 3 programmable clock generator 5P49V5908 datasheet table 1:pin descriptions number name description 1 out10b output complementary output clock 10. low-power hcsl (lp-hcsl) output. 2 xout input crystal osc illator interface output. 3 xin/ref input crystal osc illator interface i nput, or single-ended lvcmos clock input. ensure that the input voltage is 1.2v max. refer to the section ?overdriving the xin/ref interface?. 4 vdda power analog functions power supply pin. connect to 1.8v. 5 vddo power connect to 1.8v. power pin for outputs 3, 5-11 6 out9 output output clock 9. low-power hcsl (lp-hcsl) output. 7 out9b output complementary output clock 9. low-power hcsl (lp-hcsl) output. 8 out8 output output clock 8. low-power hcsl (lp-hcsl) output. 9 out8b output complementary output clock 8. low-power hcsl (lp-hcsl) output. 10 out7 output output clock 7. low-power hcsl (lp-hcsl) output. 11 out7b output complementary output clock 7. low-power hcsl (lp-hcsl) output. 12 sd/oe input internal pull- down enables/disables the outputs (oe) or powers down the chip (sd). the sh bit controls the configuration of the sd/oe pin. the sh bit needs to be high for sd/oe pin to be configured as sd. the sp bit (0x02) controls the polarity of the signal to be either active high or low only when pin is configured as oe (default is active low.) weak internal pull down resistor. when configured as sd, device is shut down, differential outputs are driven high/low, and the single-ended lvcmos outputs are driven low. when configured as oe, and outputs are disabled, the outputs can be selected to be tri-stated or driven high/low, depending on the programming bits as shown in the sd/oe pin function truth table. 13 sel1/sda input internal pull- down configuration select pin, or i2c sda input as selected by out0_sel_i2cb. weak internal pull down resistor. 14 sel0/scl input internal pull- down configuration select pin, or i2c scl input as selected by out0_sel_i2cb. weak internal pull down resistor. 15 vdd power connect to 1.8v 16 vddo power connect to 1.8v. power pin for outputs 3, 5-11 17 out6 output output clock 6. low-power hcsl (lp-hcsl) output. 18 out6b output complementary output clock 6. low-power hcsl (lp-hcsl) output. 19 out5 output output clock 5. low-power hcsl (lp-hcsl) output. 20 out5b output complementary output clock 5. low-power hcsl (lp-hcsl) output. 21 vddo4 power connect to 1.8v to 3.3v. vdd supply for out4 22 out4 output output clock 4. please refer to the output drivers section for more details. 23 out4b output complementary output clock 4. please refer to the output drivers section for more details. 24 oeb 3,11 input internal pull- down active low output enable pin for outputs 3, 5, 6, 11. 1=disable outputs, 0=enable outputs. this pin has internal pull-down. 25 nc input ? do not connect 26 nc input ? do not connect 27 vddo power connect to 1.8v. power pin for outputs 3, 5-11 28 out3b output complementary output clock 3. low-power hcsl (lp-hcsl) output. 29 out3 output output clock 3. low-power hcsl (lp-hcsl) output. 30 vdd_core power connect to 1.8v 31 vdd power connect to 1.8v 32 nc input do not connect 33 oeb 7_10 input internal pull- down active low output enable pin for outputs 7-10. 1=disable outputs, 0=enable outputs. this pin has internal pull-down. 34 out2b output complementary output clock 2. please refer to the output drivers section for more details. 35 out2 output output clock 2. please refer to the output drivers section for more details. 36 vddo2 power connect to 1.8v to 3.3v. vdd supply for out2 37 out1b output complementary output clock 1. please refer to the output drivers section for more details. type
programmable clock generator 4 revision b 07/13/15 5P49V5908 datasheet pin descriptions (cont.) pll features and descriptions spread spectrum to help reduce electromagnet ic interference (emi), the 5P49V5908 supports spread spectrum modulation. the output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system emi. the 5P49V5908 implements spread spectrum using the fractional-n output divide, to achieve controllable modulation rate and spreading magnitude. the spread spectrum can be applied to any output divider and any spread amount from 0.25% to 2.5% center spre ad and -0.5% to -5% down spread. table 2: loop filter pll loop bandwidth range depends on the input reference frequency (fref) and can be set between the loop bandwidth range as shown in the table below. table 3: configuration table this table shows the sel1, sel0 settings to select the configuration stored in otp. four configurations can be stored in otp. these can be factory programmed or user programmed. at power up time, the sel0 and sel1 pins must be tied to either the vdda powe r supply so that they ramp with that supply or are tied low (this is the same as floating the pins). this will cause the register config uration to be loaded that is selected according to table 3 above. providing that out0_sel_i2cb was 1 at por and otp register 0:7=0, after the first 10ms of operation the levels of the selx pins can be changed, either to low or to the same level as vdda. the selx pins must be driven with a digital signal of < 300ns rise/fall time and only a single pin can be changed at a time. after a pin level change, the device must not be interrupted for at least 1ms so that the new values have time to load and take effect. if out0_sel_i2cb was 0 at por, alternate configurations can only be loaded via the i2c interface. number name description 38 out1 output output clock 1. please refer to the output drivers section for more details. 39 vddo1 power connect to 1.8v to 3.3v. vdd supply for out1 40 nc input ? do not connect 41 out11 output output clock 11. low-power hcsl(lp-hcsl) output. 42 out11b output complementary output clock 11. low-power hcsl(lp-hcsl) output. 43 vddo power connect to 1.8v. power pin for outputs 3, 5-11 44 vdd power connect to 1.8v 45 oe_buffer input internal pull- up active high output enable for outputs 3, 5-11. 0=disable outputs. 1=enable outputs. this pin has internal pull-up. 46 vddo0 power power supply pin for out0_sel_i2cb. connect to 1.8 to 3.3v. sets output voltage levels for out0. 47 out0_sel_i2cb output internal pull- down latched input/lvcmos output. at power up, the voltage at the pin out0_sel_i2cb is latched by the part and used to select the state of pins 13 and 14. if a weak pull up (10kohms) is placed on out0_sel_i2cb, pins 13 and 14 will be configured as hardware select pins, sel1 and sel0. if a weak pull down (10kohms) is placed on out0_sel_i2cb or it is left floating, pins 13 and 14 will act as the sda and scl pins of an i2c interface. after power up, the pin acts as a lvcmos reference output. 48 out10 output output clock 10. low-power hcsl (lp-hcsl) output. epad gnd gnd connect to ground pad type input reference frequency?fref (mhz) loop bandwidth min (khz) loop bandwidth max (khz) 5 40 126 350 300 1000 out0_sel_i2cb @ por sel1 sel0 i 2 c access reg0:7 config 100no00 101no01 110no02 111no03 0 x x yes 1 i2c defaults 0xxyes00
revision b 07/13/15 5 programmable clock generator 5P49V5908 datasheet crystal input (xin/ref) the crystal used should be a fundamental mode quartz crystal; overtone crystals should not be used. a crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. when the oscillator load capacitance matches the crystal load capacitance, the oscillation frequency will be accurate. when the oscillator load capacitance is lower than the crystal load capacitance, the oscillation frequency will be higher than nominal and vice versa so for an accurate oscillation frequency you need to make sure to match the oscillator load capacitance with the crystal load capacitance. to set the oscillator load capacitance there are two tuning capacitors in the ic, one at xin and one at xout. they can be adjusted independently but commonly the same value is used for both capacitors. the value of each capacitor is composed of a fixed capacitance amount plus a variable capacitance amount set with the xtal[5:0] register. adjustment of the crystal tuning capacitors allows for maximum flexibility to accommod ate crystals from various manufacturers. the range of tuning capacitor values available are in accordance with the following table. xtal[5:0] tuning capacitor characteristics the capacitance at each crystal pin inside the chip starts at 9pf with setting 000000b and can be increased up to 25pf with setting 111111b. the step per bit is 0.5pf. you can write the following equation for this capacitance: ci = 9pf + 0.5pf xtal[5:0] the pcb where the ic and the crystal will be assembled adds some stray capacitance to each crystal pin and more capacitance can be added to each crystal pin with additional external capacitors. you can write the following equations for the total capacitance at each crystal pin: c xin = ci 1 + cs 1 + ce 1 c xout = ci 2 + cs 2 + ce 2 ci 1 and ci 2 are the internal, tunable capacitors. ci 1 and cs 2 are stray capacitances at each crystal pin and typical values are between 1pf and 3pf. ce 1 and ce 2 are additional external capacitors that can be added to increase the crystal load capacitance beyond the tuning range of the internal capacitors. however, increasing the load capacitance reduces th e oscillator gain so please consult the factory when adding ce 1 and/or ce 2 to avoid crystal startup issues. ce 1 and ce 2 can also be used to adjust for unpredictable stray capacitance in the pcb. the final load capacitance of the crystal: cl = c xin c xout / (c xin + c xout ) for most cases it is reco mmended to set the value for capacitors the same at each crystal pin: c xin = c xout = cx cl = cx / 2 the complete formula when the capacitance at both crystal pins is the same: cl = (9pf + 0.5pf xtal[5:0] + cs + ce) / 2 example 1 : the crystal load capacitance is specified as 8pf and the stray capacitance at each crystal pin is cs=1.5pf. assuming equal capacitance value at xin and xout, the equation is as follows: 8pf = (9pf + 0.5pf xtal[5:0] + 1.5pf) / 2 0.5pf xtal[5:0] = 5.5pf xtal[5:0] = 11 (decimal) example 2 : the crystal load capacitance is specified as 12pf and the stray capacitance cs is unknown. footprints for external capacitors ce are added and a worst case cs of 5pf is used. for now we use cs + ce = 5pf and the right value for ce can be determined later to make 5pf together with cs. 12pf = (9pf + 0.5pf xtal[5:0] + 5pf) / 2 xtal[5:0] = 20 (decimal) parameter bits step (p f) min (pf) max (pf) xtal 6 0.5 9 25 ?
programmable clock generator 6 revision b 07/13/15 5P49V5908 datasheet otp interface the 5P49V5908 can also store its configuration in an internal otp. the contents of the device's internal programming registers can be saved to the otp by setting burn_start (w114[3]) to high and can be loaded back to the internal programming registers by setting usr_rd_start(w114[0]) to high. to initiate a save or restore using i 2 c, only two bytes are transferred. the device address is issued with the read/write bit set to ?0?, followed by the appropriate command code. the save or restore instruction exec utes after the stop condition is issued by the master, during which time the 5P49V5908 will not generate acknowledg e bits. the 5P49V5908 will acknowledge the instructions af ter it has completed execution of them. during that time, the i 2 c bus should be interpreted as busy by all other users of the bus. on power-up of the 5P49V5908, an automatic restore is performed to load the otp contents into the internal programming registers. the 5P49V5908 will be ready to accept a programming instruction once it acknowledges its 7-bit i 2 c address. availability of prim ary and secondary i 2 c addresses to allow programming for multiple devices in a system. the i 2 c slave address can be changed from the default 0xd4 to 0xd0 by programming the i2c_addr bit d0. versaclock 5 programming guide provides detailed i 2 c programming guidelines and register map. sd/oe pin function the polarity of the sd/oe signal pin can be programmed to be either active high or low with the sp bit (w16[1]). when sp is ?0? (default), the pin becomes active low and when sp is ?1?, the pin becomes active high. the sd/oe pin can be configured as either to shutdown the pll or to enable/disable the outputs. the sh bit contro ls the configuration of the sd/oe pin the sh bit needs to be high for sd/oe pin to be configured as sd . when configured as sd, device is shut down, differential outputs are driven high/low, and the single-ended lvcmos outputs are driven low. when configured as oe, and outputs are disabled, the outputs are driven high/low. table 4: sd/oe pin fu nction truth table output divides each output divide block has a synchronizing por pulse to provide startup alignment between outputs divides. this allows alignment of outputs for low skew performance. this low skew would also be realized between outputs that are both integer divides from the vco frequency. this phase alignment works when using configuration with sel1, sel0. for i 2 c programming, i 2 c reset is required. an output divide bypass mode (divide by 1) will also be provided, to allow multiple buffered reference outputs. each of the four output divide s are comprised of a 12 bit integer counter, and a 24 bit fractional counter. the output divide can operate in integer divide only mode for improved performance, or utiliz e the fractional coun ters to generate a clock frequency accurate to 50 ppb. each of the output divides also have structures capable of independently generating spread spectrum modulation on the frequency output. the output divide also has the capability to apply a spread modulation to the output frequency. independent of output frequency, a triangle wave modulation between 30 and 63khz may be generated. for all outputs, there is a bypass mode, to allow the output to behave as a buffered copy of the input. sd/oe input sp sh oen osn global shutdown outn sh bit sp bit osn bit oen bit sd/oe outn 0 0 0 x x tri-state 2 0 0 1 0 x output active 0 0 1 1 0 output active 0 0 1 1 1 output driven high low 0 1 0 x x tri-state 2 0 1 1 0 x output active 0 1 1 1 0 output driven high low 0 1 1 1 1 output active 1 0 0 x 0 tri-state 2 1 0 1 0 0 output active 1 0 1 1 0 output active 1 1 0 x 0 tri-state 2 1 1 1 0 0 output active 1 1 1 1 0 output driven high low 1x x x 1 output driven high low 1 note 1 : global shutdown note 2 : tri-state regardless of oen bits
revision b 07/13/15 7 programmable clock generator 5P49V5908 datasheet output skew for outputs that share a common output divide value, there will be the ability to skew outputs by quadrature values to minimize interaction on the pcb. the skew on each output can be adjusted from 0 to 360 degrees. skew is adjusted in units equal to 1/32 of the vco period. so, for 100 mhz output and a 2800 mhz vco, you can select how many 11.161ps units you want added to your skew (resulting in units of 0.402 degrees). for example, 0, 0.402, 0.804, 1.206, 1.408, and so on. the granularity of the skew adjustment is always dependent on the vco period and the output period. output drivers the out1 to out4 clock outputs are provided with register-controlled output drivers. by selecting the output drive type in the appropriate register, any of these outputs can support lvcmos, lvpecl, hcsl or lvds logic levels the operating voltage ranges of each output is determined by its independent output power pin (v ddo ) and thus each can have different output voltage levels. output voltage levels of 2.5v or 3.3v are supported for differential hcsl, lvpecl operation, and 1. 8v, 2.5v, or 3.3v are supported for lvcmos and differential lvds operation. each output may be enabled or disabled by register bits. when disabled an output will be in a logic 0 state as determined by the programming bit table shown on page 6. lvcmos operation when a given output is configur ed to provide lvcmos levels, then both the outx and outx b outputs will toggle at the selected output frequency. all the previously described configuration and control apply equally to both outputs. frequency, phase alignment, voltage levels and enable / disable status apply to both the outx and outxb pins. the outx and outxb outputs can be selected to be phase-aligned with each other or inverted relative to one another by register programming bits. selection of phase-alignment may have negative effects on the phase noise performance of any part of the device due to increased simultaneous switching noise within the device. device start-up & reset behavior the 5P49V5908 has an internal power-up reset (por) circuit. the por circuit will remain acti ve for a maximum of 10ms after device power-up. upon internal por circuit expi ring, the device will exit reset and begin self-configuration. the device will load inte rnal registers using the configuration stored in the internal one-time programmable (otp) memory. once the full confi guration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the pll to the selected source and begin operation. power up ramp sequence vdda and vdd must ramp up together. vdd0-1, vddo4, vdd_core and vddo must ramp up before, or concurrently with, vdd0-1, vddo4, vdd_ core and vddo. all power supply pins must be connected to a power rail even if the output is unused. all power supplies must ramp in a linear fashion and ramp monotonically. vddo0-2, vddo4, vdd_core and vddo vdda
programmable clock generator 8 revision b 07/13/15 5P49V5908 datasheet i 2 c mode operation the device acts as a slave device on the i 2 c bus using one of the two i 2 c addresses (0xd0 or 0xd4) to allow multiple devices to be used in the sys tem. the interface accepts byte-oriented block write and block read operations. two address bytes specify the register address of the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). read and write block transfers can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is received, at wh ich point, all data received in the block write will be written simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-down resistors ha ve a size of 100k ? typical. i 2 c slave read and write cycle sequencing current ? read s dev ? addr ? + ? r a data ? 0 a data ? 1 a a data ? n abar p sequential ? read s dev ? addr ? + ? w a data ? 0 a data ? 1 a a data ? n abar p reg ? start ? addr a sr dev ? addr ? + ? r a sequential ? write s dev ? addr ? + ? w a data ? 0 p a data ? 1 a a data ? n a from ? master ? to ? slave from ? slave ? to ? master reg ? start ? addr a s ? = ? start sr ? = ? repeated ? start a ? = ? acknowledge abar= ? none ? acknowledge p ? = ? stop
revision b 07/13/15 9 programmable clock generator 5P49V5908 datasheet table 5: i 2 c bus dc characteristics table 6: i 2 c bus ac characteristics note 1: a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 2; i2c inputs are 5v tolerant. symbol parameter conditions min typ max unit v ih input high level for sel1/sda pin and sel0/scl pin. 0.7xvddd 5.5 2 v v il input low level for sel1/sda pin and sel0/scl pin. gnd-0.3 0.3xvddd v v hys hysteresis of inputs 0.05xvddd v i in input leakage current -1 30 a v ol output low voltage i ol = 3 ma 0.4 v symbol parameter min typ max unit f sclk serial clock frequency (scl) 10 400 khz t buf bus free time between stop and start 1.3 s t su:start setup time, start 0.6 s t hd:start hold time, start 0.6 s t su:data setup time, data input (sda) 100 ns t hd:data hold time, data input (sda) 1 0s t ovd output data valid from clock 0.9 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t f fall time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t high high time, clock (scl) 0.6 s t low low time, clock (scl) 1.3 s t su:stop setup time, stop 0.6 s
programmable clock generator 10 revision b 07/13/15 5P49V5908 datasheet table 7: absolute maximum ratings stresses above the ratings listed below ca n cause permanent damage to the 5P49V5908. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaran teed only over the recommended operating temperature range. table 8: recommended operation conditions table 9: input capacitance, lvcmos outp ut impedance, and internal pull-down resistance (t a = +25 c) item rating supply voltage, v dda , v ddd , v ddo 3.465v inputs xin/ref 0v to 1.2v voltage swing outputs, v ddo (lvcmos) -0.5v to vddo+ 0.5v outputs, i o (sda) 10ma package thermal impedance, ja 42c/w (0 mps) package thermal impedance, jc 41.8c/w (0 mps) storage temperature, t stg -65c to 150c esd human body model 2000v junction temperature 125c symbol parameter min typ max unit v ddx power supply voltage for supporting 1.8v outputs 1.71 1.8 1.89 v v dda analog power supply voltage. use filtered analog power supply if available. 1.71 1.89 v t a operating temperature, ambient -40 85 c c load_out maximum load capacitance (3.3v lvcmos only) 15 pf f in external reference crystal 8 40 mhz t pu power up time for all vdds to reach minimum specified voltage (power ramps must be monotonic) 0.05 5 ms symbol parameter min typ max unit cin input capacitance (sd/oe, sel1/sda, sel0/scl) 37pf pull-down resistor 100 300 k ? rout lvcmos output driver impedance (vddo = 1.8v, 2.5v, 3.3v) 17 ? xin / re f programmable capacitance at xin/ref 925pf xo ut programmable capacitance at xout 925pf
revision b 07/13/15 11 p rogrammable clock generator 5P49V5908 datasheet table 10:crystal characteristics note: typical crystal used is idt 603-25-150 or fox 603-25-150 . for different reference crystal options please go to www.foxonline.com . table 11: dc electrical characteristics outputs features and descriptions out1/out1b, out2/out2b, and out4/out4b can form three output pairs. each output pair has individually programmable frequencies and can be configur ed as one differential pair (l vds, lvpecl, regular hcsl) or two lvcmos outputs. vddo is individually selectable from 1.8v to 3.3v for lvds and lvcmos , and 2.5v to 3.3v for lvpecl and regular current-mode hcsl outputs. out3, 5-11 are 8 low-power hcsl(lp-hcsl) differential output pa irs. they are the same frequency which can be individually programmed. they utilize the 1.8v lp-hcsl technology wh ich can reduce supply current and terminat ion resistor count. lp-hcsl outputs are from 1mhz to 200mhz and other differential outputs are from 1mhz to 350mhz. parameter test conditions minimum typical maximum units mode of oscillation frequency 8 25 40 mhz equivalent series resistance (esr) 10 100 ? shunt capacitance 7pf load capacitance (cl) @ <=25 mhz 6 8 12 pf load capacitance (cl) >25m to 40m 6 8 pf maximum crystal drive level 100 w fundamental symbol parameter test conditions min typ max unit iddcore 3 core supply current 100 mhz on all outputs, 25 mhz refclk 44 ma lvpecl, 350 mhz, 3.3v vddox 42 47 ma lvpecl, 350 mhz, 2.5v vddox 37 42 ma lvds, 350 mhz, 3.3v vddox 18 21 ma lvds, 350 mhz, 2.5v vddox 17 20 ma lvds, 350 mhz, 1.8v vddox 16 19 ma hcsl, 250 mhz, 3.3v vddox, 2 pf load 29 33 ma hcsl, 250 mhz, 2.5v vddox, 2 pf load 28 33 ma lvcmos, 50 mhz, 3.3v, vddox 1,2 16 18 ma lvcmos, 50 mhz, 2.5v, vddox 1,2 14 16 ma lvcmos, 50 mhz, 1.8v, vddox 1,2 12 14 ma lvcmos, 200 mhz, 3.3v vddox 1 36 42 ma lvcmos, 200 mhz, 2.5v vddox 1,2 27 32 ma lvcmos, 200 mhz, 1.8v vddox 1,2 16 19 ma iddpd power down current sd asserted, i2c programming 10 14 ma 1. single cmos driver active. 2. measured into a 5? 50 ohm trace with 2 pf load. 3. iddcore = idda+ iddd, no loads. iddox output buffer supply current
programmable clock generator 12 revision b 07/13/15 5P49V5908 datasheet table 12: dc electrical characteristics for 3.3v lvcmos (v ddo = 3.3v5%, ta = -40c to +85c) 1 1. see ?recommended operating conditions? table. table 13: dc electrical char acteristics for 2.5v lvcmos (v ddo = 2.5v5%, ta = -40c to +85c) table 14: dc electrical char acteristics for 1.8v lvcmos (v ddo = 1.8v5%, ta = -40c to +85c) symbol parameter test conditions min typ max unit voh output high voltage ioh = -15ma 2.4 vddo v vol output low voltage iol = 15ma 0.4 v iozdd output leakage current (out1,2,4) tri-state outputs, vddo = 3.465v 5a iozdd output leakage current (out0) tri-state outputs, vddo = 3.465v 30 a vih input high voltage single-ended inputs - sd/oe 0.7xvddd vddd + 0.3 v vil input low voltage single-ended inputs - sd/oe gnd - 0.3 0.3xvddd v vih input high voltage single-ended input out0_sel_i2cb 2 vddo0 + 0.3 v vil input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v vih input high voltage single-ended input - xin/ref 0.8 1.2 v vil input low voltage single-ended input - xin/ref gnd - 0.3 0.4 v t r /t f input rise/fall time sd/oe, sel1/sda, sel0/scl 300 ns symbol parameter test conditions min typ max unit voh output high voltage ioh = -12ma 0.7xvddo v vol output low voltage iol = 12ma 0.4 v iozdd output leakage current (out1,2,4) tri-state outputs, vddo = 2.625v 5a iozdd output leakage current (out0) tri-state outputs, vddo = 2.625v 30 a vih input high voltage single-ended inputs - sd/oe 0.7xvddd vddd + 0.3 v vil input low voltage single-ended inputs - sd/oe gnd - 0.3 0.3xvddd v vih input high voltage single-ended input out0_sel_i2cb 1.7 vddo0 + 0.3 v vil input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v vih input high voltage single-ended input - xin/ref 0.8 1.2 v vil input low voltage single-ended input - xin/ref gnd - 0.3 0.4 v t r /t f input rise/fall time sd/oe, sel1/sda, sel0/scl 300 ns symbol parameter test conditions min typ max unit v oh output high voltage ioh = -8ma 0.7 xv ddo v ddo v v ol output low voltage iol = 8ma 0.25 x v ddo v output leakage current (out1,2,4) tri-state outputs, vddo = 3.465v 5 output leakage current (out0) tri-state outputs, vddo = 3.465v 30 v ih input high voltage single-ended inputs - sd/oe 0.7 * v ddd v ddd + 0.3 v v il input low voltage single-ended inputs - sd/oe gnd - 0.3 0.3 * v ddd v v ih input high voltage single-ended input out0_sel_i2cb 0.65 * v ddo 0v ddo 0 + 0.3 v v il input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v v ih input high voltage single-ended input - xin/ref 0.8 1.2 v v il input low voltage single-ended input - xin/ref gnd - 0.3 0.4 v t r /t f input rise/fall time sel0/scl 300 ns i ozdd a
revision b 07/13/15 13 p rogrammable clock generator 5P49V5908 datasheet table 15: dc electrical characteristics for lvds (v ddo = 3.3v+ 5% or 2.5v+ 5%, ta = -40c to +85c) table 16: dc electrical ch aracteristics for lvds (v ddo = 1.8v+ 5%, ta = -40c to +85c) table 17: dc electrical ch aracteristics for lvpecl (v ddo = 3.3v+ 5% or 2.5v+ 5%, ta = -40c to +85c) symbol parameter min typ max unit v ot (+) differential output voltage for the true binary state 247 454 mv v ot (-) differential output voltage for the false binary state -247 -454 mv v ot change in v ot between complimentary output states 50 mv v os output common mode voltage (offset voltage) 1.125 1.25 1.375 v v os change in v os between complimentary output states 50 mv i os outputs short circuit current, v out + or v out - = 0v or v ddo 924ma i osd differential outputs short circuit current, v out + = v out - 612ma symbol parameter min typ max unit v oh output voltage high, terminated through 50 ? tied to v dd - 2 v v ddo - 1.19 v ddo - 0.69 v v ol output voltage low, terminated through 50 ? tied to v dd - 2 v v ddo - 1.94 v ddo - 1.4 v v swing peak-to-peak output voltage swing 0.55 0.993 v symbol parameter min typ max unit v ot (+) differential output voltage for the true binary state 247 454 mv v ot (-) differential output voltage for the false binary state -247 -454 mv ? v ot change in vot between complimentary output states 50 mv v os output common mode voltage (offset voltage) 0.8 0.875 0.95 v ? v os change in vos between complimentary output states 50 mv i os outputs short circuit current, v out + or v out - = 0v or v dd 924ma i osd differential outputs short circuit current, v out + = v out -612ma
programmable clock generator 14 revision b 07/13/15 5P49V5908 datasheet table 18: electrical char acteristics ? dif 0.7v regular hcsl outputs (ta = -40c to +85c) (for out1, out2 and out4 programmable differential output pairs when configured as hcsl outputs.), ta = t com or t i nd; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1 4 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 20 % 1, 2, 4 voltage high v hi gh 660 850 1,7 voltage low v low -150 150 1,7 max voltage vmax 1150 1 min voltage vmin -300 1 vswing vswing scope averaging off 300 mv 1,2,7 crossing voltage (abs) vcross_abs scope averaging off 250 550 mv 1,5,7 crossing voltage (var) -vcross scope averaging off 140 mv 1, 6 2 measured from differential waveform 1 guaranteed by design and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting ? - vcross to be smaller than vcross absolute. 7 at default smbus settings. statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv
revision b 07/13/15 15 p rogrammable clock generator 5P49V5908 datasheet table 19: electrical char acteristics?low power hc sl (lp-hcsl) outputs (for out3 and out5?11 lp-hcs l differential output pairs.) ta = tamb; supply voltage per vdd, vddio of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes slew rate t rf scope averaging on 1 2.5 4 v/ns 1,2,3 slew rate matching dv/dt slew rate matching, scope averaging on 7 20 % 1,2,4 voltage high v high 660 0 850 7 voltage low v low -150 0 150 7 max voltage vmax 0 1150 7 min voltage vmin -300 0 7 vswing vswing scope averaging off 300 0 mv 1,2 crossing voltage (abs) vcross_abs scope averaging off 250 0 550 mv 1,5 crossing voltage (var) ? -vcross scope averaging off 0 140 mv 1,6 2 measured from differential waveform 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting ? -vcross to be smaller than vcross absolute. 7 at default smbus settings. statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production.
programmable clock generator 16 revision b 07/13/15 5P49V5908 datasheet table 20: ac timing el ectrical characteristics (v ddo = 1.8v 5%, ta = -40c to +85c) (spread spectrum generation = off) symbol parameter test conditions min. typ. max. units input frequency limit (xin) 840mhz input frequency limit (ref) 1200mhz output frequency single ended clock output limit (lvcmos) 1200 differential clock output limit 1 350 f vco vco frequency vco operating frequency range 2500 2800 3000 mhz f pfd pfd frequency pfd operating frequency range 1 1 150 mhz f bw loop bandwidth input frequency = 25mhz 0.06 0.9 mhz t2 input duty cycle duty cycle 45 55 % all differential outputs except reference output 45 50 55 % measured at vdd/2, all outputs except reference output 2.5v and 3.3v 45 50 55 % measured at vdd/2, all outputs except reference output 1.8v 40 50 60 % measured at vdd/2, reference output (150.1mhz - 200mhz) with 50% input 40 50 60 % measured at vdd/2, reference output(s) (120.1mhz - 200mhz) 30 50 70 % slew rate, slew[1:0] = 00 1.5 2.6 4.0 slew rate, slew[1:0] = 01 1.3 2.4 3.8 slew rate, slew[1:0] = 10 1.2 2.3 3.7 slew rate, slew[1:0] = 11 1.0 2.2 3.6 slew rate, slew[1:0] = 00 1.0 1.7 2.7 slew rate, slew[1:0] = 01 0.8 1.5 2.5 slew rate, slew[1:0] = 10 0.7 1.4 2.45 slew rate, slew[1:0] = 11 0.6 1.3 2.39 slew rate, slew[1:0] = 00 1.5 2.6 4.0 slew rate, slew[1:0] = 01 1.3 2.4 3.8 slew rate, slew[1:0] = 10 1.2 2.3 3.75 slew rate, slew[1:0] = 11 1.0 2.2 3.67 rise times lvds, 20% to 80% 300 fall times lvds, 80% to 20% 300 rise times lvpecl, 20% to 80% 400 fall times lvpecl, 80% to 20% 400 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vdd=3.3v v/ns single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vdd=2.5v single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vdd=1.8v t5 ps f in 1 input frequency f out mhz t3 output duty cycle t4
revision b 07/13/15 17 p rogrammable clock generator 5P49V5908 datasheet table 21: pci express ji tter specifications (v ddo = 1.8v + 5%, t a = -40c to +85c) (for lp-hcsl(out3, out5-11) outputs) note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. 1. peak-to-peak jitter after applying syst em transfer function for the common clock ar chitecture. maximum limit for pci express gen 1. 2 . rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture and reporting the worst case results for each evaluation band. maximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). 3. rms jitter after applying system transfer function for the common clock architecture. this specification is based on the pci _express_base_r3.0 10 nov, 2010 specification, and is subject to change pending the final re lease version of the specification. 4. this parameter is guaranteed by c haracterization. not tested in production. cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switching, differential outputs 46 ps cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switching, lvcmos outputs 74 ps rms phase jitter (12khz to 5mhz integration range) reference clock (out0), 25 mhz lvcmos outputs 0.5 ps rms phase jitter (12khz to 20mhz integration range) differential output, 25mhz crystal, 156.25mhz on out2, and 100mhz lp-hcsl outputs on out3, out5-11. 0.75 1.5 ps output skew between out1, out2, out4 skew between the same frequencies , with outputs using the same driver format and phase delay set to 0 ns. 75 ps output skew between out3 and out5-11 skew between outputs at same frequency and conditions 49.5 84 ps t8 3 startup time pll lock time from power-up, measured after all vdd's have raised above 90% of their target value. 10 ms t9 4 startup time pll lock time from shutdown mode 34ms 5. spread spectrum generation is of f unless otherw ise stated. 4. actual pll lock time depends on the loop configuration. t6 clock jitter t7 1. practical low er f requency is determined by loop f ilter settings. 2. a slew rate of 2.75v/ns or greater should be selected f or output f requencies of 100mhz or higher. 3. includes loading the conf iguration bits f rom eprom to pll registers. it does not include eprom programming/w rite time. symbol parameter conditions min typ max pcie industry specification units notes t j (pcie gen1) phase jitter peak- to-peak ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 23.85 86 ps 1,4 t refclk_hf_rms (pcie gen2) phase jitter rms ? = 100mhz, 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 1.83 3.1 ps 2,4 t refclk_lf_rms (pcie gen2) phase jitter rms ? = 100mhz, 25mhz crystal input low band: 10khz - 1.5mhz 0.54 3 ps 2,4 t refclk_rms (pcie gen3) phase jitter rms ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 0.51 1 ps 3,4
programmable clock generator 18 revision b 07/13/15 5P49V5908 datasheet table 22: pci express ji tter specifications (v ddo = 3.3v5% or 2.5v5%, t a = -40c to +85c) (for regular hcsl(out1, out2 and out4) outputs) note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. 1. peak-to-peak jitter after applying syst em transfer function for the common clock ar chitecture. maximum limit for pci express gen 1. 2 . rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture and reporting the worst case results for each evaluation band. maximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). 3. rms jitter after applying system transfer function for the common clock architecture. this specification is based on the pci _express_base_r3.0 10 nov, 2010 specification, and is subject to change pending the final re lease version of the specification. 4. this parameter is guaranteed by c haracterization. not tested in production. table 23: spread spectrum generation specifications symbol parameter conditions min typ max pcie industry specification units notes t j (pcie gen1) phase jitter peak- to-peak ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 30 86 ps 1,4 t refclk_hf_rms (pcie gen2) phase jitter rms ? = 100mhz, 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 2.56 3.10 ps 2,4 t refclk_lf_rms (pcie gen2) phase jitter rms ? = 100mhz, 25mhz crystal input low band: 10khz - 1.5mhz 0.27 3.0 ps 2,4 t refclk_rms (pcie gen3) phase jitter rms ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 0.8 1.0 ps 3,4 symbol parameter description min typ max unit f out output frequency output frequency range 1 300 mhz f mod mod frequency modulation frequency khz amount of spread value (programmable) - center spread amount of spread value (programmable) - down spread 0.25% to 2.5% -0.5% to -5% 30 to 63 f spread spread value %f out
revision b 07/13/15 19 p rogrammable clock generator 5P49V5908 datasheet 5P49V5908 referen ce schematic 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a layout notes: 1. separate xout and xin traces by 3 x the trace width 2. do not share crystal load capacitor ground via with other components. 3. route power from bead through bulk capacitor pad then through 0.1uf capacitor pad then to clock chip vdd pad. 4. do not share ground vias. one ground pin one ground via. revision history: 0.1 3/26/2015 first publication lvds termination 3.3v lvpecl termination 2.5v and 3.3v hcsl termination lvcmos termination manufacture part number z@100mhz pkgsz dc res. current(ma) fair-rite 2504021217y0 120 0402 0.5 200 murata blm15ag221sn1 220 0402 0.35 300 murata blm15bb121sn1 120 0402 0.35 300 tdk mmz1005s241a 240 0402 0.18 200 tecstar tb4532153121 120 0402 0.3 300 note:ferrite bead fb1, fb2= lp hcsl termination for out3/3b, out5/5b to out11/11b the following pins have weak pull-down resistors: 12,13,14,33,24 and 47 place near i2c controller if used note: vcc can be set to 1.8v,2.5v or 3.3v fg_x1 out_0_sel-i2c v1p8vcb outr0 v1p8vcb outr1 outrb1 v1p8vcb outr2 outrb2 outr3 outrb3 v1p8vcb outr4 outrb4 outr2 out_2 fg_x2 sda scl v1p8vca v1p8vc v1p8vca outr5 outrb5 outr6 outrb6 outr7 outrb7 outr8 outrb8 outr9 outrb9 outr10 outrb10 outr11 outrb11 oe_buffer oeb7_10 oeb3,11 sd/oe v1p8vca v1p8vcb v1p8vc outr3 outrb3 out_0_sel-i2c sda scl v1p8vc v1p8vca vcc vcc1p8 v1p8vc v3p3 size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 26, 2015 5P49V5908_sch san jose, ca size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 26, 2015 5P49V5908_sch san jose, ca size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 26, 2015 5P49V5908_sch san jose, ca r3 100 1 2 u2 receiver 1 2 r12 50 1 2 u7 receiver 1 2 r5 49.9 1% 1 2 c10 .1uf 1 2 u4 receiver 1 2 c9 10uf 1 2 r14 33 1 2 c8 .1uf 1 2 fb2 signal_bead 1 2 r11 50 1 2 r7 10k 1 2 c11 .1uf 1 2 r10 50 1 2 c1 10uf 1 2 c5 .1uf 1 2 r8 10k 1 2 r2 2.2 1 2 fb1 signal_bead 1 2 r6 33 1 2 c3 .1uf 1 2 r4 49.9 1% 1 2 c4 .1uf 1 2 u5 5P49V5908a xout 2 xin/ref 3 nc 32 vddo 5 out7 10 sel1/sda 13 sel0/scl 14 sd/oe 12 vdda 4 vdd 15 vddo0 46 out0_sel_i2cb 47 vddo1 39 out1 38 out1b 37 vddo2 36 out2 35 out2b 34 vdd_core 30 out3 29 out3b 28 vddo4 21 out4 22 out4b 23 epad 49 epad 50 epad 51 epad 52 epad 53 epad 54 epad 55 epad 56 out5b 20 out5 19 vddo 27 out6b 18 out6 17 out7b 11 nc 25 nc 26 vdd 31 vdd 44 vddo 43 nc 40 oeb7_10 33 oe_buffer 45 out8 8 out8b 9 out9 6 out9b 7 out10 48 out10b 1 out11 41 out11b 42 oeb3,11 24 vddo 16 epad 57 epad 58 r15 33 1 2 r18 10k 1 2 c7 np 1 2 c2 1uf 1 2 r13 33 1 2 r17 33 1 2 r16 33 1 2 gnd gnd y1 25.000 mhz cl = 8pf 4 1 2 3 u3 receiver 1 2 c6 np 1 2 idt 603-25-150 25.000mhz cl=8pf
programmable clock generator 20 revision b 07/13/15 5P49V5908 datasheet test circuits and loads outx v dda clk out gnd c l 0.1f v ddox 0.1f v ddd 0.1f 33 hcsl output 33 50 50 hcsl differential output test load 2pf 2pf zo=100ohm differential rs rs low-power differential output test load 2pf 2pf 5 inches zo=100ohm alternate differential output terminations rs zo units 33 100 27 85 ohms
revision b 07/13/15 21 p rogrammable clock generator 5P49V5908 datasheet typical phase noise at 100mhz (3.3v, 25c) note : all outputs operational at 100mhz , phase noise plot with spurs on.
programmable clock generator 22 revision b 07/13/15 5P49V5908 datasheet overdriving the xin/ref interface lvcmos driver the xin/ref input can be overdr iven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xout pin can be left floating. the amplitude of the input signal should be between 500mv and 1.2v and the slew rate should not be less than 0.2v/ns. figure general diagram for lvcmos driver to xtal input interface shows an example of the interface diagram for a lvcmos driver. this configuration has three properties; the total output impedance of ro and rs matches the 50 ohm transmission line impedance, the vrx voltage is generated at the clkin inputs which maintains the lv cmos driver voltage level across the transmission line for best s/n and the r1-r2 voltage divider values ensure that the clock level at xin is less than the maximum value of 1.2v. general diagram for lvcmos driver to xtal input interface table 24 nominal voltage divider va lues vs lvcmos vdd for xin shows resistor values that ensure the maximum drive level for the xin/ref port is no t exceeded for all combinations of 5% tolerance on the driver vdd, the versaclock vdda and 5% resistor toleranc es. the values of the resistors can be adjusted to reduce the loading for slower and weaker lvcmos driver by increasing the voltage divider attenuation as long as the minimum drive level is maintained over all tolerances. to assist this as sessment, the total load on the driver is included in the table. table 24: nominal voltage divider values vs lvcmos vdd for xin ? xout xin / ref r1 r2 c3 0. 1 uf v_ xin lv cmos vdd ro ro + rs = 50 o hms rs zo = 50 ohm lvcmos driver vdd ro+rs r1 r2 v_xin (peak) ro+rs+r1+r2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242
revision b 07/13/15 23 p rogrammable clock generator 5P49V5908 datasheet lvpecl driver figure general diagram for lv pecl driver to xtal input interface shows an example of the interface diagram for a +3.3v lvpecl driver. this is a standard lvpecl termination with one side of the driver f eeding the xin/ref input. it is recommended that all components in the schematics be placed in the layout; though some components might not be used, they can be utilized fo r debugging pu rposes. the datasheet specifications are c haracterized and guaranteed by using a quartz crystal as the input. if the driver is 2.5v lvpecl, the only change necessary is to use the appropriate value of r3. table 25 nominal voltage divider values vs driver vdd shows resistor values that ensu re the maximum drive level for the clkin port is not exceeded for all combinations of 5% tolerance on the driver vdd, the versaclock vddo_0 and 5% resistor tolerances . the values of the resistors can be adjusted to reduce the loading for slower and weaker lvcmos driver by increasing the impedance of the r1-r2 divider. to assist this assessment, the total load on the driver is included in the table. table 25: nominal voltage divi der values vs driver vdd ? +3 .3 v lv pe cl dr iv er zo = 50 ohm zo = 50 ohm r1 50 r2 50 r3 50 xout xin / ref c1 0. 1 uf lvcmos driver vdd ro+rs r1 r2 vrx (peak) ro+rs+r1+r2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242
programmable clock generator 24 revision b 07/13/15 5P49V5908 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? . and 132 ? . the actual value should be select ed to match the differential impedance (zo) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? . differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the rece iver as possible. the standard termination schematic as shown in figure standard termination or the termination of figure optional termination can be used, which uses a center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. in addition , since these outputs are lvds compatible, the input receiver's amplitude and common-mode input range should be verified for compatibility with the idt lvds output. if using a non-standard termination, it is recommended to contact idt and confirm that the termination will function as in tended. for ex ample, the lvds outputs cannot be ac coupled by placing capacitors between the lvds outputs and the 100 ohm shunt load. if ac coupling is required, the coupling caps must be placed between the 100 ohm shunt termination and the receiver. in this manner the termination of the lvds output remains dc coupled lvds driver lvds driver lvds receiver lvds receiver z t c z o ? z t z o ? z t z t 2 z t 2 standard termination optional termination
revision b 07/13/15 25 p rogrammable clock generator 5P49V5908 datasheet pci express application note pci express jitter analysis me thodology models the system response to reference clock jit ter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the ji tter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase interpolator in the receiver. these transfer functions are called h1, h2, and h3 respec tively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiver is the result of applying this system transfer fu nction to the clock spectrum x(s) and is: in order to generate time doma in jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen1 magnitude of transfer function for pci express gen2, two transfe r functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen2a magnitude of transfer function pcie gen2b magnitude of transfer function for pci express gen 3, one transfer function is defined and the evaluation is performed ov er the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
programmable clock generator 26 revision b 07/13/15 5P49V5908 datasheet pcie gen3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference cl ock requirements. marking diagram 1. ?ddd? denotes the dash code. 2. ?g? denotes rohs compliance. 3. ?i? denotes industrial temperature. 4. ?yyww? is the two last digits of the ye ar and week that the part was assembled. 5. ?#? denotes the stepping code. 6. ?$? denotes mark code. 7. ?lot? denotes lot number. idt5p49v59 08adddndgi #yyww$ lot
revision b 07/13/15 27 p rogrammable clock generator 5P49V5908 datasheet package outline and pack age dimensions ndg48 (48-pin vfqfpn)
programmable clock generator 28 revision b 07/13/15 5P49V5908 datasheet package outline and pack age dimensions ndg48 (48-pin vfqfpn), cont.
revision b 07/13/15 29 p rogrammable clock generator 5P49V5908 datasheet ordering information ?ddd? denotes the dash code. ?g? after the two-letter package code denotes pb-free configuration, rohs compliant. revision history part / order number shipping packaging package temperature 5P49V5908adddndgi trays 48-pin vfqfpn -40 to +85c 5P49V5908adddndgi8 tape and reel 48-pin vfqfpn -40 to +85c rev. date originator description of change a 06/24/15 b. chandhoke initial release. b 07/13/15 b. chandhoke 1. added conditions text and min/max values for vih/vil. 2. updated 1.8v, 2.5v, and 3.3v vih/vil conditions text and min/max values for "single-ended inputs - clksel, sd/oe" 3. changed name of parameter "lock time" to "startup time" 4. added idt and fox crystal references.
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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